Description
1. The goal of this problem is to make you familiar with the SystemC environment, in particular
compilation and simulation of SystemC code, using the simple FIFO example. Follow the instructions in the file
instructionsSystemC.pdf to set up your environment and run the simple FIFO example (simple/simple_fifo.cpp).
Inspect the sources of the example and the included Makefile to understand SystemC compilation and simulation
process, experiment with the Makefile usage and start modifying the example to experiment with different features of
the SystemC language:
(a) Briefly explain (in 2-3 sentences) the functionality and structure of the example. Report the output from
simulation of the example. (20 points)
(b) Modify the example to replace the custom fifo channel with a corresponding sc_fifo
the standard SystemC channel library. Simulate the code to verify correctness. Finally, report the output and
submit the modified source code. (30 points)
(c) Look at the example code in simple_perf.cpp file (perf folder). In this implementation, we evaluate the
impact of the fifo size on the average transfer time per character across the producer and consumer (reported
in pico-seconds). Analyze the fifo buffer for varying buffer sizes [1, 5, 10, 20,25, 50, 75, 90, 100] and report
on the trend that you can observe. (30 points)
2. This system consists of a 14-tap finite impulse response (FIR) filter which feeds the output to an accumulator (both
the filter and accumulator are within the green block shown). On each positive clock edge, the FIR filter receives data,
collects it in a buffer and performs the filtering operation. An internal accumulator module sums up each cycle’s filter
results write the result into memory (see Figure 1). The FIR operation can be mathematically written as:
y[n] = x[n]*b0 + x[n-1]*b1 + … x[n-i]*bi + … x[n-N]*bN
The filter coefficients of the FIR filter are as follows: {472, 34, 348, 181, 295, 361, 430, 260, 179, 151, 81, 68,78,
302}. Write SystemC code that simulates the system till the entirety of the data in memory is passed through the FIR
filter, and filtered outputs are obtained. The provided code has the memory and the orchestration main.cpp written.
You are to write the FIR filter and connect it to the system so that the correct output (as in result.log) is generated.
3.In this question, you will explore how SystemC can be used to simulate system level components
and analyze their output. I2C is a serial data transfer protocol developed for inter chip communication. I2C mainly
consists of two wires, SDA (used for address/data transfer), and SCL (used for clocking the devices). In the I2C
protocol, there is a master chip, and a multitude of slave chips. All the devices are connected to SDA and SCL as
shown in Figure 2. When a master chip wants to send or receive data from a slave chip, it sends a
followed by
gets activated and receives data and sends an ACK back to the master in the above mentioned format.
In the q3_i2c folder, the code for an I2C master, an I2C slave device, and a test bench are given. Before you run make,
set the following environment variable:
#bash shell
export SC_SIGNAL_WRITE_CHECK=DISABLE
#csh shell
setenv SC_SIGNAL_WRITE_CHECK DISABLE
The test bench establishes an I2C master-slave communication and sends a data value from the master to the slave.
Figure 2 shows an example of a master and slave nodes in I2C. The result of this communication can be observed in
output VCD files. You can use gtkwave to view the generated waveforms.vcd output file:
> gtkwave waveforms.vcd &
If you do not have gtkwave, install it on your linux machine with:
> sudo apt install gtkwave
Figure 3 shows the timing diagram in gtkwave for a single slave only (Note you have to add the signals and zoom out
to see the waveforms as shown in the figure). As you can see in the figure, the data is transmitted after enable is mad
3
high, and rst is made low. The address is sent on the addr line, and the transmitted data is saved at the master (seen in
saved_data strobe). The data is then sent and received at the slave node(seen in slave1_data_in strobe).
Figure 2. I2C bus-based system
Figure 3. GTKWave output of I2C system
Modify the code for the i2c example to add three other slaves to the system and use the test bench to send four data
values (one to each slave) from the master. The code also requires modifications so that sc_trace may be used to
capture data to and from all slave modules. The data values to be sent from the master node are shown in the
expected_signals.png file, keep in mind these values are in hexadecimal format. Generate a similar output as Figure
3 for your design and explain what you see on the VCD file of your output (the signals to capture are given in the
expected_signals.png file). The modifications needed are annotated with [Missing] statements in files.
4. In this question, you will implement a Transaction Level Model (TLM) for memory access (reads
and writes) requests made by an initiator module that is connected with two memory modules. The memory modules
of different sizes share a contiguous address space. The q4_tlm folder, contains partial implementations for two
models, one that uses SystemC Signals (in the sysc sub-folder) and the other uses SystemC TLM (in the tlm sub-folder)
to communicate. First complete the SystemC Signals implementation (in the sysc sub-folder) by filling in the missing
code (indicated by TODO) to make the appropriate connections between the modules as hinted in the top.h file. Run
the simulation by varying the values of the NUM_ITER variable (in the constants.h file) across {2×10 1, 2×10 2, 2×10 3,
2×10 4, 2×10 5 }. Record the time taken for each simulation run (using the Linux ‘time’ utility or code annotations in
the main file). The tlm folder contains a similar implementation of the same design. At this point, fill out the missing
code for the connections (top.h) and TLM transactions (in initiator.h and target.h). Vary the number of iterations as
in the previous simulation. Record the time for execution for each case. Plot your execution time (y-axis) with respect
to NUM_ITER (x-axis) for both implementations in a single graph, and comment on the trend you notice (highlight
the difference in execution time between TLM and signal-accurate models).
• Please submit your solutions via Canvas. Submissions should include source code files in a single zip file,
with separate folders designated for every problem.
• Some questions might not have a clearly correct or wrong answer. In such cases, grading is based on your
arguments and reasoning for arriving at a solution.
• Please submit your responses as a single PDF file for all question responses
