Description

You have to do the Step 2 and Step 3.Step 2: Create the Verilog RTL and simulate a simple 4-bit multiplier based on the

Verilog in lecture slide 11. Make sure you register all inputs before you use them and

your simulations show that if is fully functional. Synthesize the multiplier.

1. Does the hardware implementation match what you expect? Please comment

why/why not.

2. What is the maximum clock frequency for the multiplier?

3. What is the total area for the multiplier?

Step 3: Create the Verilog RTL and simulate a pipelined 4-bit multiplier based on

lecture slides 13-17. Make sure you register all inputs before you use them and your

simulations show that if is fully functional. Note that you will need to make a simple FSM

to control the pipelined multiplier. Synthesize the multiplier.

1. Does the hardware implementation match what you expect? Please comment

why/why not.

2. What is the maximum clock frequency for the multiplier?

3. What is the total area for the multiplier?

Unformatted Attachment Preview

High-Level VLSI Design Methodology

Lecture 4:

Multiplication

Dr. Matthew LaRue

Contents

• Motivation

• Multiplication overview

• Multiplication in Verilog

• Pipelined multipliers

• Improved multipliers

2

Motivation

• Multiplication is a key operation for almost all ICs

• CPUs

• GPUs

• Digital signal processing (DSP)

• Machine Learning (ML) and Artificial Intelligence (AI)

• Multiplication operations are difficult to implement in hardware

• High area

• High power

• Slow

• Typical CPU: 1 clock cycle for addition, 10 clock cycles for

multiplication

3

MAC Functions

• Multiply-accumulate (MAC) operations are a fundamental component in

various signal processing operations

• Important benchmark for DSP processors

• Many FPGAs have special hardware to optimize MAC functions

MAC implementation of filter

4

Multiplication – Base 10

• Reminder of base 10 multiplication is useful for understanding binary

multiplication

Step 1: 4375×7

factors

4375

x 467

??????

multiplicand

multiplier

4375

x 467

30625

Step 3: 4375×4

4375

x 467

30625

26250

17500

Partial product

product

Step 2: 4375×6

4375

x 467

30625

26250

Step 4: Add partial products

4375

x 467

30625

26250

+ 17500

2043125

5

Multiplication – Base 2

• Truth table for binary multiplication

Multiplicand

0

0

Multiplier

0

1

Product

0

0

1

1

0

1

0

1

6

Multiplication – Base 2

• Base 2 multiplication is mostly the same as base 10 multiplication

00110

x 00101

??????

multiplicand

Step 1: 00110×1

Step 3: 00110×1

00110

00101

00110

00110

x 00101

00110

00000

00110

multiplier

x

Partial product

Step 2: 00110×0

00110

x 00101

00110

00000

(sanity check: 6×5

= 30

0011110 = 30)

Step 4: Add partial products

4375

x 467

00110

00000

+ 00110

0011110

7

Multiplication – Negative Numbers

• Two’s complement numbers – can have multiplication issues with dealing

with large numbers and negative numbers if not implemented correctly

• Correct way on next slide

+

0111

x 1100

0000

0000

0111

0111

1010100

7

x -4

-28

Wrong answer!

-44

8

Multiplication – Negative Numbers

• Need to sign extend multiplicand and multiplier

• Multiplicand = length m

• Multiplier = length n

• Extended length = (m + n)

• Final product will be length 2(m+n), but we only use the lowest (m+n) bits

• Multiply two 4-bit numbers = 8-bit result

00000111

0111

00000111

x 11111100

x 1100

x 11111100

00000000

????

????????

00000000

00000111

00000111

00000111

00000111

00000111

+ 00000111

-28 correct!!!

000011011100100

9

Multiplication – 2n Numbers

• Special multiplication case: multiplying by a 2n value is just an n-bit shift

left operation

• Multiply by 23 (8) results in a 3-bit shift left

• The same as base 10 multiplication by 10n value

• Multiply by 103 value results in a shift by 3 places

Base 10 – 10n multiplier

Base 2 – 2n multiplier

123

x 1000

123000

1101

x 01000

1101000

10

Multiplication – Verilog

• Need to make factors and

product of multiplication

signed values for

multiplication work correctly

• By default Verilog

assumes unsigned, will

lead to incorrect result

• Can also uses $signed()

system task on a factor to

tell Verilog to interpret value

as signed

• Make sure length(product) =

length(multiplicand) +

length(multiplier)

module mult_ver(

input wire clk,

input wire rst_n,

input wire signed [3:0] a,

input wire signed [3:0] b,

output reg signed [7:0] c

);

always @(posedge clk or negedge rst_n)

begin

if (rst_n == 1’b0) begin

c

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