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CSE/EEE 230 – Bonus 4
Important: This is an individual assignment. Please do not collaborate.
Make sure to follow the academic integrity policies. Using work done by someone else will be
considered a violation of the academic integrity and will result in a report to the Dean’s office.
Your work should not match with anything found online.
Copying any part of this assignment, and providing them to another person or posting them on
the Internet without a permission of the instructor will be a violation of its copyright.
http://www.asu.edu/copyright/
No late submissions will be accepted.
Show all the steps including how you arrived at your solution to receive full credit.
There is one question that counts towards Bonus points, if you turn it in. It will be graded for
10 points and scaled down to 1 point.
The following MIPS Code is executed using the MIPS pipeline architecture. Include all iterations
of the loop.
Start:
Loop:
addi $s0, $s1, 32
lb $t1, 0($s0)
sb $t1, 2($s0)
nor $t2, $t1, $t1
sb $t2, 0($s0)
addi $s0, $s0, -8
bne $s0, $s1, Loop
Exit:
Question: Loop Unrolling – For the above code, show the steps in unrolling the loop and write the
2-issue VLIW pipeline representing the order of issuing the instructions from the loop unrolled
code.
CSE/EEE 230 – Assignment 8
Important: This is an individual assignment. Please do not collaborate.
Make sure to follow the academic integrity policies. Using work done by someone else will be
considered a violation of the academic integrity and will result in a report to the Dean’s office.
Your work should not match with anything found online.
Copying any part of this assignment, and providing them to another person or posting them on
the Internet without a permission of the instructor will be a violation of its copyright.
http://www.asu.edu/copyright/
No late submissions will be accepted.
Show all the steps to receive full credit.
There are 2 questions. The score will be scaled down to a total of 3 points.
Make sure to segment your document for the 3 questions.
The following MIPS Code is executed using the MIPS pipeline architecture. Include all iterations
of the loop.
Start:
Loop:
Exit:
addiu $s1, $0, 0x1234
addi $s0, $0, 0x122C
lb $t1, 0($s0)
sb $t1, 2($s0)
nor $t2, $t1, $t1
sb $t2, 0($s0)
addi $s0, $s0, 4
bne $s0, $s1, Loop
addi $s0, $0, 0x122C
Question 1: Pipeline – For the above code, write the Pipeline Implementation by resolving all the
three hazards. (20 points). Consider the following assumptions: (structural, data and control
hazards are resolved using hardware)
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There is separate instruction and data memory access.
Register read and write can happen within the same clock cycle.
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There is Forwarding unit. Show data forwarding between the correct stages, wherever
necessary.
There is Hazard detection Unit and a 2-bit Prediction Unit along with Branch Target
Buffer, i.e., resolution for control hazards using all the hardware modifications discussed.
There is Hazard detection Unit to detect mispredictions and flush if necessary.
The 2-bit branch prediction scheme is used with initial prediction being weakly Not Taken.
There is Branch target Buffer (BTB) containing target address for the branch instruction.
Use stall if an instruction is delayed after fetch.
Use nop if an instruction is delayed before fetch.
Question 2: Exception Handling: Show the pipeline implementation, including exception
handling and all iterations of the loop. (10 points) For hazard resolution:
•
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•
•
•
•
•
•
There is separate instruction and data memory access.
Register read and write can happen within the same clock cycle.
There is Forwarding unit. Show data forwarding between the correct stages, wherever
necessary.
There is Hazard detection Unit, a static Prediction Unit along with Branch Target Buffer.
There is Hazard detection Unit to detect mispredictions and flush if necessary.
The static branch prediction scheme always predict Not Taken Path.
There is Branch target Buffer (BTB) containing target address for the branch and jump
instructions.
Use stall if an instruction is delayed after fetch.
Use nop if an instruction is delayed before fetch.
For the following MIPS Code, assume that an Arithmetic Overflow Exception Occurs at the
“sub” instruction.
Start:
Loop:
Exit:
addi $t9, $0, 1
addi $t8, $0, 32
addiu $s1, $s0, 1
slt $t0, $s1, $s0
bne $t0, $0, Exit
lbu $t1, 0($s0)
sub $t1, $t1, $t8
sb $t1, 0($s0)
add $s0, $s0, $t9
j Loop
addi $s0, $s1, -1
Consider the following Exception Routine:
Routine:
sw $k0, 1008($0)
sw $k1, 1012($0)
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