Description
Hi, I wanted to know if you would be able to complete part 2 by 6PM EST on 11/7/23? A tutor worked on part 1 but I need someone to do part 2. For part 2 you need to have pspice
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ECE3124
Project #2 – Fall 2023
Class A Two-Stage Amplifier Design
Design a two-stage BJT class-A power amplifier
This project is an individual effort, similar designs will not be graded
Transistor – 2N2222 or equivalent
Transistor Specifications:
Parameter
Power Dissipation, PD
Current Gain,
Small Signal, ro
Minimum
Nominal
100
200
infinite
Function Generator Specifications:
Parameter
Minimum
Frequency for vin
Resistor Specifications:
Parameter
Resistance
Power Dissipation, PD
Minimum
1 ohm
Maximum
600 mW
300
Nominal
1 kHz
Maximum
Nominal
Maximum
1 MEGAohm
3W
Two-Stage Amplifier Performance Specifications with 200 unless otherwise noted:
Note: any of the following parameters labeled with “**” is a secondary goal and extra points if
your design achieves the goal.
Parameter
DC Power Supply Voltage, VCC (use selected Voltage
from Project #1)
DC Power Supply Current, IPS (for both stages)
Load resistance, RL, capacitive coupled
Peak‐to‐Peak Current swing at RL, ,
, no clipping
Small signal current gain, ,
at
**Small signal gain stability, , over 100
**Small signal input resistance, Rin
**Power Efficiency,
200
Minimum
+5 VDC
Nominal
Maximum
+30 VDC
250 mA
64 ohm
100 mA
102
300
110
,
118
+/‐ 15%
5 k
5%
50 k
HINT:
Design the input stage to your two-stage amplifier by (1) adding another transistor circuit
to the beginning of your Project 1 power amplifier and design using the two transistors
together, OR, (2) the preferred method, by using the equivalent input resistance, RIN*, of
your Project 1 as the “load” to this new amplifier as shown in the figure below. Using the
approach in (2), you will need to translate the current gain and maximum swing specs to
the equivalent circuit using iL* and RIN. Note that in either design procedure; remove the
Rev 0.0
ECE3124
Project #2 – Fall 2023
Class A Two-Stage Amplifier Design
voltage source and 1 kΩ source resistor used during the design of the Project 1 as shown
below.
Design Notes:
To change the value in CircuitLab, select Q2N2222 and change “B_F” to the value
required.
To change the value in OrCAD, select Q2N2222 in “Eval” library and right mouse
click on transistor to edit the “PSpice Model”. Change the value for f .
Resistors can have any value at this point in the design. You don’t need to adhere to
industry standard values unless you want to (could be helpful later). If you calculate a
resistor of 2 ohms or less, then you probably don’t need this one.
When calculating the DC operation of your circuit, it could be helpful to approximate
the Input Driver VBEQ = 0.7V and the Power Amp (Project #1) VBEQ = 0.8V.
There will be differences between your hand calculations and the PSpice results.
Enter you hand-calculated resistors into PSpice and slightly adjust the resistor(s) until
you achieve the required specifications in PSpice.
When performing a transient analysis, it is best to set “maximum step size” to
0.01msec and simulate over a range of 3 msec.
PART 1: HAND CALCULATIONS
Note: If you changed your original Power Amp Project #1 design as the result of Lab #3
or other reason, then re-simulate the Power Amp circuit using the new circuit and
include here.
A. From project #1, list the following values in a Table. Use the Project #1 design with
standard resistor values (the one you built in the Lab #3 experiment).
1. Equivalent input resistance, Rin, for that power amp stage using your PSpice
results. Note: this value already includes the 64 ohm load.
2. Small Signal Gain. Use the PSpice value of small signal current gain for just the
Project #1 power amp stage.
Rev 0.0
ECE3124
Project #2 – Fall 2023
Class A Two-Stage Amplifier Design
3. VCC. You will be using the same DC voltage from the power amplifier (Project
#1) for this driver amplifier (Project #2)
B. Submit all hand calculations for your design. It is important to show how you decided
on your resistor values and DC operating conditions. Use = 200 for all of the
following calculations.
C. What are your calculated DC transistor bias parameters? Make one table showing ICQ,
VBEQ, VCEQ, and PD for each transistor (hand calculations for this design and PSpice
parameters for project #1).
D. What is your total DC current, IPS, supplied from the DC voltage source? You can add the
total current for the hand calculations of this design and that of PSpice for Project #1.
E. What is your calculated small signal current gain, Ai? Make a table of the calculated gain
for this driver (input) stage, the power amp stage (PSpice Projcct #1), and the combined
two-stage design (multiply the two gains together).
F. Using a value of = 200, calculate your Input Resistance, Rin, for the complete two-stage
design. The calculated value will require that you include the small signal equivalent
models for both the driver and the power amp.
G. In a table, list the resistor values and associated power dissipation for all resistors in your
design. Split the table into resistors in the driver amplifier stage and the power amplifier
stage.
H. Submit the complete schematic of your two-stage design.
PART 2: PSPICE SIMULATIONS: Here you will be simulating the complete two-stage
amplifier. Use the PSpice model for Project #1 that uses standard resistor values.
A. SCHEMATIC: Submit your complete PSpice schematic. All resistor values must
clearly be shown on the schematic.
B. SIMULATED DC BIAS: What are the simulated DC bias parameters, ICQ, VCEQ, VBEQ
and transistor Power Dissipation, PD, transistor? Submit a table showing the simulated
values for ICQ, VCEQ, VBEQ, and PD, transistor for each transistor.
C. SIMULATED POWER SUPPLY BIAS: What is the total current delivered from the
supply, IPS? Does your circuit operate below the specification for maximum current, IPS <
250mA.
D. SIMULATED CURRENT SWING: Simulate your design in PSpice using a 1kHz
sinusoidal input, use a voltage source with a 10K source resistor as shown above. Place a
current probe on the wire leading into your circuit (on the left side of the capacitor, C1).
What is the largest peak-to-peak swing in the output current, iL, through the 64 ohm load
resistance? To find the maximum swing, you should slowly increase the source amplitude
until the output current waveform begins to clip at the top or the bottom. Unless you have
a design optimized for maximum symmetrical swing, it’s most likely that the clipping will
not be symmetrical. In other words, the point of clipping in the positive peak current will
be different from the negative peak current. Submit a plot showing iL with clipping using
a = 200. When clipping occurs, chose the smaller of the two values and double this
value, this is the peak-to-peak swing in the output current, iL. Clearly report this peak-topeak swing in the output current, iL. Did your design achieve the 100mA peak-to-peak
swing (50 mA peak)?
Rev 0.0
ECE3124
Project #2 – Fall 2023
Class A Two-Stage Amplifier Design
E. Repeat (D) for = 100 and 300. Submit a table showing the maximum peak-to-peak
swing in iL for = 100, 200 and 300. Did you meet the peak-to-peak swing under all
conditions?
F. SIMULATED EFFICIENCY: Using the peak swing in load current, iL (just below
clipping), and load resistance, 64 ohms, calculate the simulated power conversion
efficiency, ? You will need the total power supply current, IPS, from your simulation.
Show all your calculations using data recorded from your simulated plots. Show all your
calculations using data recorded from your simulated plots, no points for just an answer.
G. SIMULATED SMALL SIGNAL OPERATION: Using PSpice, reduce the input source
amplitude so that it is should be small enough to operate your transistor in the small signal
region. Verify that the peak AC voltage across the Base-Emitter (B-E) junction, vbe, is less
than 2.6mV peak (
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