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Need help with solving all the questions in Lab 5. Also working in, Xilinx Software and also Logic Designer.
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LAB 5
DECODER AND 7-SEGMENT DISPLAY
4.1
Objectives
To demonstrate the application of a decoder with a 7-segment digital display.
4.2
Background
You are to design an 8421 BCD code converter to drive a 7-segment indicator. The four inputs to the
converter network (A,B,C,D) represent an 8421 binary-coded decimal digit. Even though there are
16 combinations for a four-input network, assume that only input combinations representing 0
through 9 can occur as inputs, so the remaining six unused combinations don’t care. Figure 5.1 shows
a typical network driving a 7-segment display module. The details of a BCD decoder and a 7-segment
are separately discussed as follows:
7-Segment Indicator
Logic design often requires circuits to transmit data to human operators. A 7-segment indicator is
frequently used to display any one of the decimal digits 0 through 9. A typical network driving 7segment display module is shown in Figure 5.1. For example, one is indicated by lighting segments
b and c (see Figure 5.2), and two by lighting segments a, b g, e, and d. A segment is lighted when a
logic 1 is applied to the corresponding input on the display module. Figure 5.2 shows the PIN for a
SEC5010 7-segment display module to be used for your experiment. However, this experiment leaves
pin 5, which is connected to the decimal point. Pins 3 and 8 are the connections for the ground.
7-Segment Display Circuit
The network in Figure 5.1 is usually designed with the use of a BCD to 7-segment Decoder. A decoder
generates all of the minterms of all the input variables. For instance, a 4-input decoder generates all
of the 16 minterms of input variables. However, only combinations representing 0- 9 are allowed for
a BCD decoder.
Data Input
In the experiment, you must also use mechanical switches for data entry. There are a large number of
mechanical switches available. Figures 5.3a and 5.3b illustrate a single-pole/single-throw (SPST)
switch and a single-pole/double-throw (SPDT) switch. Figures 4.4a and 4.4b show how a switch and
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a pull-up resistor to +5V provides a signal compatible with TTL circuits for the two basic switch
configuration.
When the switch is closed in Figure 5.4a, it provides an output voltage of 0V. When open, it gives a
voltage V=5V – IR where I is the logical 1 current required by the load connected to the switch output.
The value R limits the power dissipated when the switch is closed and provides a logical 1 voltage at
the required input current of the load when it is open. We will be using SPST switches.
The mechanical switch used in the experiment is a DIP switch. A dip switch consists of several SPST
switches in one package. A typical dip switch configuration is shown in Figure 5.5.
In this experiment, you are first to build a 7-segment display module using a BCD decoder with Xilinx
Software for verification. Then a 7-segment display circuit is built by using a dip-switch for data
entries (See Figure 4.7).
7- Segment Decoder
A 7-segment decoder is not available in the symbol library of Xlinix software, so we will design
one. We will create the Decoder with active high outputs for a common cathode display. The lit
display segments for each digit from 0 to 9 are given in the following truth table
Table 5.1: Truth table for a 7-segment decoder with active-high outputs
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Inputs
D2 D1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
N
0
1
2
3
4
5
6
7
8
9
Inv
Inv
Inv
Inv
Inv
Inv
a
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
b
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
15
c
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
Outputs
d
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
e
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
f
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
g
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
Note that the outputs of this Decoder are all LOW for invalid (inv) BCD codes. Based on the above
truth table, we derive the Boolean equations for the outputs using K–maps or Boolean algebra.
a = D3 D1 + D2 D1 D0 + D3 D 2 D1 + D 3 D2 D0
b = D3 D 2 + D 2 D1 + D3 D1 D0 + D3 D1 D0
c = D3 D2 + D2 D1 + D3 D0
d = D2 D1 D0 + D 3 D 2 D1 + D 3 D1 D 0 + D 3 D2 D1 D0
e = D2 D1 D 0 + D 3 D1 D 0
f = D2 D1 D0 + D 3 D2 D1 + D 3 D2 D 0 + D3 D 2 D1
g = D 3 D 2 D1 + D 3 D2 D1 + D3 D 2 D1 + D 3 D1 D 0
= 1 3+ 1 2 3 + 1 2 3 + 0 1 2 + 0 1 2 3
4.4
Procedure
Part I: 7-segment Decoder Simulation Circuit Using Xilinx
Please study the 7-segment Decoder before you do this section.
1. Set up the necessary truth table.
2. Implement the Decoder using Xilinx Schematic Capture. Using macros for the design is
strongly encouraged. Figure 5.6 shows a typical design using macros.
3. Verify the operation and capture the appropriate graphs/diagrams to validate your design.
Part II: 7-segment Decoder Circuit
1. Look up the 74LS48 BCD to 7-segment decoder/driver in your data book. Study and
understand the functionality of this chip.
2. Draw and implement a circuit that uses a 74LS48 BCD to a 7-segment decoder to display the
decimal equivalent of a 4-bit BCD number on a 7-segment display (SEC5010). Note that all
unused pins of 74LS48 are connected to Vcc .
3. Use a DIP switch to input the values. Be sure to correctly hook up these switches.
4. Record output display for all input combinations using the DIP switch, including those invalid
inputs.
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4.5
Study Questions
1. What patterns are produced for inputs 10 to 15 in Part I.4?
2. Comment on the simulated results using Xilinx Software in your Part I with that in Part II.
3. Comment on the differences in circuit designed for the Decoder using Xilinx with that shown
in TTL data book.
4.6
Equipment
1. Logic Designer x1
2. Xilinx software x1
3. Components: 74LS157 x1, SEC5010 x1, 74LS48 x1, 8-bit DIP Switch x1,
330 ohm resistor x8
4.7
References
1. Richard S. Sandige, Digital Design Essentials, Prentice Hall, 2002
2. Xilinx Student Edition Foundation Series Software
3. TTL Logic Data Book, Texas Instruments, 1988.
A
B
C
D
Figure 5.1 A 7-segment display circuit
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Figure 5.2 A SEC5010
Figure 5.3a A SPST switch
VCC
Figure 5.3b A SPDT switch
VCC
Figure 5.4a A SPST with a pull-up resistor
Figure 5.4b A SPDT with a pull-up resistor
Figure 5.5 A DIP switch with pull-up resistor
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Dip-Switch
D,C,B,A
Decoder
X1-X7
7-Segment
Figure 4.6 A typical design using macors
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Figure 4.7 A simple decoder with a 7-segment display
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