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do homework 8 and 9. homework in PDFs below. I attached an example of how the answer pdf should look like.
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ENGE 240 Digital Systems
Homework 8
Notes:
• Each problem worth 1 point. Deduction of points will be made for any incorrect and/or
incomplete work
• Let me know if you have questions on problem interpretation or if you believe there is a
possible error in the test.
• Ensure to give all problems your best effort and show your deriving procedure to get full
points.
• Attach extra paper with your work to the end if more space is needed.
• Ensure to turn in one file with file name in the format of ENGE240_HWX_First name_Last
Name.pdf. For example: ENGE240_HW1_Michael_Tyler.pdf
8.1.Write the output expression for each circuit below, and simplify your result.
8.2.Draw the circuit diagram using AND gates, OR gates, or combination of both to implement
the following logic expressions as stated. Ensure least number of gates are used.
( ) =
( ) = + + ( ) = ( ) = ( + )
( ) = ( + ) + ( + + )
8.3.Draw the circuit diagram using only NAND gates to implement the following logic
expressions as stated. Ensure least number of gates are used.
̅̅̅̅̅̅̅̅̅̅
( ) = +
( ) = ( ) = ̅ + + (
+ )( + ̅̅̅̅
)
( ) = ̅[ + ̅ ( + )]
̅ + ̅ + ̅̅̅̅
( ) = ̅
8.4. Draw the circuit diagram using only NOR gates to implement the following logic
expressions as stated. Ensure least number of gates are used.
̅ + ̅ +
̅̅̅̅
̅̅̅̅̅̅
( ) = ̅̅̅̅
+ ̅̅̅̅
( ) = ̅
( ) =
( ) = ( + )( + )
̅̅̅̅ + ̅̅̅̅
( ) = [ (
) + ̅̅̅̅̅̅
]
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8.5.Simplify the circuit in figure below as much as possible, and verify the simplified circuit is
equivalent to the original by showing that the truth tables are identical.
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ENGE 240 Digital Systems
Homework 9
Notes:
• Each problem worth 1 point. Deduction of points will be made for any incorrect and/or
incomplete work
• Let me know if you have questions on problem interpretation or if you believe there is a
possible error in the test.
• Ensure to give all problems your best effort and show your deriving procedure to get full
points.
• Attach extra paper with your work to the end if more space is needed.
• Ensure to turn in one file with file name in the format of ENGE240_HWX_First name_Last
Name.pdf. For example: ENGE240_HW1_Michael_Tyler.pdf
9.1. For the parallel adder below, determine the complete sum by analysis of the logical
operation of the circuit. Verify your result by long hand addition of the two input numbers.
Ensure to use formula to calculate first.
9.2. For each set of binary numbers below, determine the output states for the comparator as
shown below. Ensure to use formula to calculate.
(a) A3A2A1A0=1100, B3B2B1B0=1001
(b) A3A2A1A0=1000, B3B2B1B0=1011
(c) A3A2A1A0=0100, B3B2B1B0=0100
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9.3.For the multiplexer in figure below, determine the output for the following input states:
D0=0, D1=1, D2=1, D3=0, S0=1, S1=0. Ensure to use formula to calculate.
9.4. Try to use the NAND gate(s) to design a 4-variable voting system. The output is 1 only when
three or four input variables are 1. For other case, the output is 0. Ensure to show the circuit
diagram with least number of gates.
9.5. Try to use the commercial look ahead carry adder 74LS283 to design a 4-bit adder/subtracter
system with following requirements.
(1) The inputs are two 4-bit binary number (i.e. a1a2a3a4, and b1b2b3b4) in SMF form.
(2) Ensure to include a control signal M. When M = 0, the system will perform addition of the
input binary numbers. When M=1, the system will perform subtraction of input binary
number.
(3) The absolute decimal value of the output sum will not be greater than 15.
(4) The output should be in 2s complement form.
(5) You can add necessary gates to the circuit, ensure least number of gates are used.
Hint: Consider converting each input to its 2s complement format before doing subtraction. To
convert to 2s complement, consider using XOR operation.
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