Description
I have attached file lab 3.and attached other files for helping
Unformatted Attachment Preview
Lab 3
Get started:
Download the lab3.zip (includes start file for starting the cadence and model file) and unzip in your working
directory (EE459 or other)
Make sure you close Cadence Virtuoso before you exit the virtual machine.
Part A:
Build a NOR gate and validate its functionality using simulation in the Cadence
virtuoso tool.
Report includes the screenshot of the schematic and waveform (highlight some
expected output with given input, like For NAND gate input A= 1, B= 0, expected output is 1.)
Cadence Tutorial
Setting Up Cadence:
1. Log in to server:
1. Download VNC Viewer, install and log into one of the vlsi servers (for example,
vlsi5.eecs.utk.edu:99 or other servers vlsi3 through vlsi7)
(https://help.eecs.utk.edu/knowledgebase/general/remote-access/vnc).
2. Make a directory called EE692 and unzip lab3.zip in EE692
3. Go to your Cadence folder and start Cadence Virtuoso using: source startcad
Build NAND Gate:
The Cadence Virtuoso “Cadence Interpreter Window” (CIW for short) will now appear somewhere
on your screen:
1. Create library:
Select file -> New -> Library
Name as tutorial, and elect attach to existing technology library (NCSU_TechLib_ami06)
2. Create Cellview:
Select file -> New -> Cell View. Name it as Nand
3. Place NMOS:
Select the place instance icon or hotkey “i”, set up as follow:
Make sure change the Model name into ami06N for NMOS
You will see highlighted yellow noms, left click to place it
4.
Place PMOS:
Repeat the NMOS step for PMOS, make sure cell is pmos4 and Model name is ami06P
5.
Place Wire :
Press “w” for wire and connect the circuit
6. Place Input Pin:
Press “P” to place Vdd, A, B
7. Place GND:
Press “i”, cell is gnd
8. Place voltage source for A, B, C
Press “i”, cell is vpulse and set up as follow for B, A
For Vdd, press “i”, cell is vdc and set up as follow for Vdd
9. Place Output Pin:
Simulation:
1. Launch ADE L:
2. Set the Simulator:
3. Setup model files:
4. Set up Analyses:
5. Save all the outputs:
6. Set up output to plot:
In the ADE L window, select Outputs -> To Be Plotted -> Select On Design. Then go to design
and click on the signal you wish to plot.
7. Save and run simulation:
Waveforms:
For input 11, NAND = 0,
Input 01, NAND = 1
Make sure you close the Candence Virtuoso
before you exit the vlsi server.
Purchase answer to see full
attachment
